1. Field of the Invention
The present invention relates to a semiconductor transistor and method for making the same, and more particularly, to a semiconductor transistor with strained source/drain regions that have a reduced interface mismatch defect, and method for making the same.
2. Description of the Prior Art
The performance of semiconductor transistors has increased year after year with the diminution of critical dimensions and the advance of large-scale integrated circuits (LSI). However, it has been recently pointed out that the miniaturization attained by a lithographic technology has reached its limit. Therefore, how to improve the carrier mobility so as to increase the speed performance of semiconductor transistors has become a major topic for study in the semiconductor field. Attempts have been made to use strained source/drain regions made of silicon germanium, for instance. In this type of semiconductor transistor, a compressive strain occurs in the channel region due to the silicon germanium which has a larger spacing than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of a conventional PMOS transistor. As shown in FIG. 1, the conventional PMOS transistor includes a substrate 10 made of monocrystalline silicon, two field isolation regions 12 positioned in the substrate 10, a gate insulating layer 14 positioned on the surface of the substrate 10, a gate 16 positioned on the gate insulating layer 14, and a channel region 18 corresponding to the gate 16 positioned in the substrate 10. The PMOS transistor further includes two lightly doped regions 20 respectively positioned alongside the channel region 18, and a source region 22 and a drain region 24 respectively positioned on opposite sides of the lightly doped regions 20. The source region 22 and the drain region 24 are P type, and made of silicon germanium in which the percentage of germanium is held constant, for example at 30%.
The conventional PMOS transistor suffers some disadvantages. First, the critical thickness of the source region and the drain region is limited to prevent the silicon germanium from peeling. In addition, interface mismatch defects tend to occur between the silicon germanium and the substrate (monocrystalline silicon) because the percentage of germanium between the source region 22 and the drain region 24 (30%), and the substrate 10 (close to 0%) is too large.